**Option A:** OR gate

**Option B:** AND gate

**Option C:** NOT gate

**Option D:** None of the above

**Correct Answer: **NOT gate ✔

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**Option A:** NAND gate

**Option B:** OR gate

**Option C:** AND gate

**Option D:** None of the above

**Correct Answer: **NAND gate ✔

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**Option A:** A & B

**Option B:** C & D

**Option C:** A & D

**Option D:** B & C

**Correct Answer: **A & B ✔

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**Option A:** PLCC

**Option B:** QFP

**Option C:** PGA

**Option D:** BGA

**Correct Answer: **BGA ✔

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**Option A:** OR operation

**Option B:** AND operation

**Option C:** NOT operation

**Option D:** None of the above

**Correct Answer: **NOT operation ✔

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**Option A:** Input operation

**Option B:** Tristate output operation

**Option C:** Bi-directional I/O pin access

**Option D:** All of the above

**Correct Answer: **All of the above ✔

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**Option A:** State Reduction

**Option B:** State Minimization

**Option C:** State Assignment

**Option D:** State Evaluation

**Correct Answer: **State Assignment ✔

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**Option A:** OR gates

**Option B:** NOT gates

**Option C:** NAND gates

**Option D:** None of the above

**Correct Answer: **NAND gates ✔

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**Option A:** 0

**Option B:** 1

**Option C:** Either 0 & 1

**Option D:** None of the above

**Correct Answer: **0 ✔

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**Option A:** NOT gate

**Option B:** OR gate

**Option C:** AND gate

**Option D:** None of the above

**Correct Answer: **NOT gate ✔

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**Option A:** Stop signal

**Option B:** Invert input signal

**Option C:** Act as a universal gate

**Option D:** None of the above

**Correct Answer: **Invert input signal ✔

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**Option A:** AND gate

**Option B:** NAND gate

**Option C:** NOT gate

**Option D:** None of the above

**Correct Answer: **NOT gate ✔

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**Option A:** (00, 01, 10, 11)

**Option B:** (00, 10, 01, 11)

**Option C:** (00, 01, 11, 10)

**Option D:** (00, 10, 11, 01)

**Correct Answer: **(00, 01, 10, 11) ✔

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**A. NOT gate**

B. OR gate

C. AND gate

D.None of the above

**Correct Answer: **NOT gate ✔

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**Option A:** 2TTL

**Option B:** 5TTL

**Option C:** 8TTL

**Option D:** 10TTL

**Correct Answer: **10TTL ✔

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**Option A:** 10 CPS

**Option B:** 120 CPS

**Option C:** 12CPS

**Option D:** None of the above

**Correct Answer: **12CPS ✔

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**Option A:** I and II

**Option B:** II and III

**Option C:** III only

**Option D:** II and III

**Correct Answer: **I and II ✔

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**Option A:** Weighted code

**Option B:** Cyclic redundancy code

**Option C:** Self-complementing code

**Option D:** Algebraic code

**Correct Answer: **Self-complementing code ✔

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**Option A:** 1 at any input causes the output to be at logic 1

**Option B:** 1 at any input causes the output to be at logic 0

**Option C:** 0 any input causes the output to be at logic 0

**Option D:** 0 at any input causes the output to be at logic 1

**Correct Answer: **1 at any input causes the output to be at logic 1 ✔

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**Option A:** an astable MV

**Option B:** a bistable MV

**Option C:** a latch

**Option D:** a monostable MV

**Correct Answer: **a latch ✔

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**Option A:** all the inputs to the gates are “1”

**Option B:** all the inputs are ‘0’

**Option C:** either of the inputs is “1”

**Option D:** all the inputs and outputs are complemented

**Correct Answer: **all the inputs and outputs are complemented ✔

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**Option A:** have lower fabrication area

**Option B:** can be used to make any gate

**Option C:** consume least electronic power

**Option D:** provide maximum density in a chip

**Correct Answer: **can be used to make any gate ✔

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**Option A:** TTLAS

**Option B:** CMOS

**Option C:** ECL

**Option D:** TTLLS

**Correct Answer: **ECL ✔

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**Option A:** logic 0 and 1 are represented by 0 and positive voltage respectively

**Option B:** logic 0 and, -1 are represented by negative and positive voltages respectively

**Option C:** logic 0 voltage level is higher than logic 1 voltage level

**Option D:** logic 0 voltage level is lower than logic 1 voltage level

**Correct Answer: **logic 0 voltage level is lower than logic 1 voltage level ✔

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**Option A:** 2n

**Option B:** 22 n

**Option C:** 2n-1

**Option D:** — 2n

**Correct Answer: **22 n ✔

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**Option A:** FFFF (hex)

**Option B:** 1111 (binary)

**Option C:** 7777 (octal)

**Option D:** All of the above

**Correct Answer: **FFFF (hex) ✔

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**Option A:** 675

**Option B:** 275

**Option C:** 572

**Option D:** 573

**Correct Answer: **275 ✔

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**Option A:** (37)10

**Option B:** ( 69)10

**Option C:** (41 )10

**Option D:** — (5)10

**Correct Answer: **(37)10 ✔

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**Option A:** Two’s complement only

**Option B:** Sign and magnitude and one’s complement only

**Option C:** Two’s complement and one’s complement only

**Option D:** All three representations

**Correct Answer: **All three representations ✔

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## Digital computers are more widely used as compared to analog computers, because they are__________?

**Option A:** less expensive

**Option B:** always more accurate and faster

**Option C:** useful over wider ranges of problem types

**Option D:** easier to maintain

**Correct Answer: **useful over wider ranges of problem types ✔

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**Option A:** 10101.001

**Option B:** 10100.001

**Option C:** 10101.010

**Option D:** 10100.111

**Correct Answer: **10101.001 ✔

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**Option A:** Base 10

**Option B:** Base 16

**Option C:** Base8

**Option D:** Base 3

**Correct Answer: **Base 3 ✔

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**Option A:** it is used by everybody

**Option B:** any logic function can be realized by NAND gates alone

**Option C:** all the minization techniques are applicable for optimum NAND gate realization

**Option D:** many digital computers use NAND gates

**Correct Answer: **any logic function can be realized by NAND gates alone ✔

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**Option A:** floating point hardware is costly

**Option B:** it is slower than software

**Option C:** it is not possible to perform floating point addition by hardware

**Option D:** of no specific reason.

**Correct Answer: **floating point hardware is costly ✔

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